As channel lengths of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) continue to shrink, many effects which are negligible in a long channel model of MOSFETs become more prominent and even become dominant factors affecting device performance. These effects are generally called short channel effects. The short channel effects tend to degrade the electrical performances of the devices. For example, the short channel effects will cause problems such as decrease of threshold voltage on a gate, increase of power consumption, and decrease of signal to noise ratio.
In order to control the short channel effects, more impurities such as phosphor and boron have to be doped in the channel. However, this will cause decrease of carrier mobility in a device channel, and further, the gradient of the distribution of the impurities doped in the channel may be difficult to control, which may instead cause serious short channel effects. Furthermore, conventional SiGe PMOS strained silicon technology has encountered a bottleneck and can hardly provide stronger strain to a channel. Moreover, the thickness of the gate oxide dielectric also encounters a bottleneck, and thus the rate of a thickness of gate oxide to become thinner can hardly keep up with reduction of gate width, causing increased leakage through gate dielectric. Critical dimensions continue to shrink, and causing resistances of source/drain regions and power consumption of devices continue to increase.
A trend in the industry is to improve conventional planar device technology to reduce a thickness of a channel region and thus to reduce an electrically neutral region at the bottom of a depletion layer in a channel, such that the depletion layer in the channel can fill the whole channel region. Devices functioning as above are called Fully Depleted devices. In contrast, conventional planar devices belong to Partially Depleted devices.
However, in order to manufacture Fully Depleted devices, the thickness of a silicon layer in a channel has to be very thin. The conventional manufacturing process, especially the conventional bulk-silicon based manufacturing process, can hardly make a structure satisfying such requirements, and is costly. Even the new SOI (silicon on insulator) process can hardly control a very thin silicon layer in a channel region. Research and development of Fully Depleted devices have turned to three-dimensional device structures, i.e., the Fully Depleted double-gate or triple-gate technology.
The three-dimensional device structures (also called vertical devices) refer to such a structure in which a cross section of source/drain is not on the same plane as that of a gate. Those structures are referred to as Fin Field Effect Transistor (FinFet) structures. In a three-dimensional device structure, a channel region is not included in bulk silicon or SOI, so a very thin fully depleted channel can be made by, for example, etching.
FIG. 1 shows a proposed three-dimensional semiconductor device. The semiconductor device comprises: a semiconductor body 20 located on an insulating layer 10; source/drain regions 30 abutting opposite first side faces 22 of the semiconductor body 20; gates 40 located on second side faces 24 of the semiconductor body 20 which are adjacent to the first side faces 22. A gate dielectric layer and a work function metal layer may be interposed between the respective gates 40 and the semiconductor body 20, but are not shown in FIG. 1. In order to reduce the resistance of source/drain regions, the end portion of the source/drain regions 30 may be expanded. Namely, the width (in the xx′ direction) of the respective source/drain regions 30 is larger than the thickness of the semiconductor body 20. However, with the increase of the width (d) of the source/drain regions 30, the parasitic capacitance between the source/drain regions 30 and the gates 40 increases, resulting in an increased resistance-capacitance delay and degraded AC performance of the device.